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RISCy Bitsness
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cpu1.v
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1992-06-18
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/*
10 29 28-24 23-19 18-0
00 0/1 l/s r r abs - sext
load r, n(r)
store r, n(r)
10 29,18-15 28-24 23-19 14-0/4-0
01 type r r v/r
add r, r, r/v
sub r, r, r/v
and r, r, r/v
or r, r, r/v
xor r, r, r/v
lt r, r, r/v
le r, r, r/v
eq r, r, r/v
lsh r, r, r/v
jmp r, r, r/v
halt r, r, r/v
10 29 28-24 23-0
10 0/1 t/f r abs
bt r, abs
bf r, abs
10 29 28-24 23-0/15-0
11 0/1 /h r v
const r, v 23-0
consth r, v 15-0
bus:
clock
reset
a31_2
d31_0
r/w
start
ack
near
*/
module cpu1(clock, reset, a, d, rw, start, ack);
input clock;
input reset;
inout [31: 0]d;
reg [31: 0]dd;
assign d = dd;
output [31: 0]a;
reg [31: 0]a;
output rw;
reg rw;
output start;
reg start;
output near;
reg near;
input ack;
reg [31: 0]r[32];
reg [31: 0]pc, b, c, res, next, i, tmp;
reg [ 4: 0]rr;
reg br;
always @(negedge clock)
if (~reset) begin
pc = 0;
start = 1;
near = 0;
r[0] = 0;
br = 0;
rr = 0;
end else begin
a = pc;
start = 0;
if (br) begin
br = 0;
pc = next;
end else begin
pc = pc + 4;
end
rw = 1;
dd = 32'bz;
@(negedge clock);
while (ack)
@(negedge clock);
start = 1;
i = d;
@(negedge clock);
case (i[31:30])
0: begin
a = r[i[28:24]]+i[18:0];
if (~i[29]) begin
rw = 1;
rr = i[23:19];
dd = 32'bz;
end else begin
rw = 0;
dd = r[i[23:19]];
rr = 0;
end
start = 0;
@(negedge clock);
while (ack)
@(negedge clock);
start = 1;
res = d;
end
1: begin
rr = i[28:24];
b = r[i[23:19]];
if (i[29]) begin
c = {17'b0,i[14:0]};
end else begin
c = r[i[4:0]];
end
case (i[18:15])
0: res = b + c;
1: res = b - c;
2: res = b&c;
3: res = b|c;
4: res = b^c;
5: res = (b < c ? 32'h80000000:32'0);
6: res = (b <= c ? 32'h80000000:32'0);
7: res = (b == c ? 32'h80000000:32'0);
8: res = (c[31]?b<<c:b>>(-c));
9: begin
res = pc;
br = 1;
next = b + c;
end
10: begin
#100
$stop;
end
endcase
end
2: begin
next = {8'b0,i[23:0]};
rr = 0;
tmp = r[i[28:24]];
br = i[29]^tmp[31];
end
3: begin
rr = i[28:24];
if (i[29]) begin
tmp = r[i[28:24]];
res = {i[15:0],tmp[15:0]};
end else begin
res = {8'b0,i[23:0]};
end
end
endcase
if (rr != 0)
r[rr] = res;
end
endmodule